Memory cells of dynamic random access memories (DRAMs) each have a storage capacitor for storage of electrical charge which characterizes the information content of the memory cell, as well as a selection transistor for addressing the storage capacitor. In the case of trench DRAM cells, the storage capacitors are in the form of trench capacitors which are oriented on hole trenches incorporated in a semiconductor substrate from one substrate surface. A first electrode or internal electrode is in this case in the form of a filling in the hole trench. The opposing or outer electrode is in the form of a doped region in a section of the semiconductor substrate which surrounds a lower section of the hole trench. The filling in the hole trench is isolated by means of a collar isolator from the surrounding semiconductor substrate in an upper section of the hole trench, which is formed between the substrate surface and the lower section. The internal electrode is isolated from the outer electrode by a capacitor dielectric that is provided on the wall of the hole trench.
The selection transistor for the memory cell is in the form of a field-effect transistor, whose active region is formed in the semiconductor substrate. The active region has two source/drain areas, which are separated by a body area. A gate electrode controls the charge carrier distribution in the body area between the two source/drain areas.
When the memory cell is not being addressed, the two source/drain areas are isolated from one another. When the memory cell is being addressed, moving charge carriers in a channel area of the body area which is adjacent to the gate dielectric are enriched by a suitable potential on the gate electrode, so that a conductive channel is formed between the two source/drain areas.
The isolation characteristics of the selection transistor when the memory cell is not being addressed are dependent on the length of the channel which connects the two source/drain areas when the memory cell is being addressed.
In conventional cell array field-effect transistors with a recessed channel (recess channel array transistor, RCAT), the two source/drain areas are arranged on a plane which is horizontal with respect to the substrate surface. The gate electrode is provided in a recess trench which is incorporated in the semiconductor substrate, between the two source/drain areas of the field-effect transistor. The distance between the two source/drain areas as well as the depth to which the recess trench is incorporated in the semiconductor substrate results in an effective channel length Leff.
An arrangement having DRAM trench memory cells and having fin field-effect transistors with a gate electrode recessed in the semiconductor substrate, as selection transistors, is described in U.S. Pat. No. 5,945,707.
German Patent Application No. 10361695.0 discloses a field-effect transistor with a curved channel (curved FET), as depicted in FIG. 1. In particular, FIG. 1 depicts a longitudinal section through a CFET on the left, and a cross section at right angles to this on the right. An active region 12 of the CFET is formed in a semiconductor fin 11 which is formed from the semiconductor substrate 1. The active region 12 has two source/drain areas 121, 122 as well a body area 123. The two source/drain areas 121, 122 are each in the form of doped regions at mutually opposite ends of the semiconductor fin, and are adjacent to a substrate surface 10 of the semiconductor substrate 1. A gate trench structure or groove filling 14 is incorporated in the semiconductor fin 11 between the two source/drain areas 121, 122. The channel length of the CFET results from the depth to which the groove filling 14 is incorporated. The body area 123 is adjacent to the two source/drain areas 121, 122 and extends to underneath the lower edge of the groove filling 14.
A gate electrode of the CFET 4 has two gate electrode sections 23, 23′ which are opposite one another on the longitudinal faces of the semiconductor fin 11 and are each isolated from the semiconductor fin 11 by a gate dielectric 20. The CFET 4 is isolated by isolator structures 2 from structures which are orthogonally adjacent to the longitudinal faces. In the longitudinal section, the gate electrode sections 23, 23′ are arranged on a plane parallel to the section plane, and are represented by dashed lines.
In a trench DRAM cell array, the selection transistors are arranged together with the storage capacitors in each case one behind the other and electrically isolated from one another to form cell rows. The cell rows are each separated from one another by one of the isolator structures 2.
During operation of the CFET 4, a conductive channel which connects the two source/drain areas 121, 122 to one another is formed by a suitable potential on the gate electrode sections 23, 23′, in a channel area 15 of the body area 123 adjacent to the gate dielectric 20. A cell current 16 flows through the channel. The length of the channel is governed essentially by the depth to which the gate trench structure 14 is incorporated. The effective channel width is governed by the extent of the gate electrode sections 23, 23′ in the direction at right angles to the substrate surface 10.
One trench capacitor is in each case arranged adjacent to one of the ends of the semiconductor fin in a trench DRAM cell. In order to connect the internal electrode of the trench capacitor to the first source/drain area, the collar isolator is re-formed in a section adjacent to the semiconductor fin, so that the internal electrode is directly adjacent to the active region of the respectively associated CFET in the area of a buried strap window. In general, a highly doped region is formed by outward diffusion of a dopant from a dopant carrier as a buried connection (buried strap) between the internal electrode and the first source/drain area.
The resistance of the buried strap is comparatively high. The disturbing influence of the comparatively high resistance becomes more pronounced the smaller the absolute dimensions of the memory cell, for example because the cross-sectional area of the buried strap window decreases.
Furthermore, two strands of mutually adjacent word lines are provided in each of the isolator structures, which each form the gate electrode sections of the selection transistors in places, and can be reliably isolated from one another. Owing to the short distance between the two word line strands, there is high coupling capacitance between mutually adjacent word lines. In order to reduce the word line series resistance, the isolator structures can be provided with a high aspect ratio, although this is technologically difficult to produce.